Active Silicon AS-PHX-D48CL-3CPCI32-B-CR Frame Grabber
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Phoenix-D48CL is a 3U CompactPCI board for the acquisition of digital data from a variety of Camera Link sources, including digital frame capture and line scan cameras. It supports all the formats of the Base and Medium configurations, i.e. single 8 to 16 bit data, through 12 bit RGB, to four tap 12 bit sources, as well as dual Base configuration, i.e. acquisition from two asynchronous Base cameras.
Phoenix-D48CL also supports various camera tap formats, such as line interlaced – adjacent lines are output simultaneously; line offset – lines are output from different parts of the CCD simultaneously; pixel interlaced – adjacent pixels on the same line are output simultaneously; and pixel offset – pixels are output from different parts of the same line simultaneously.
Phoenix-D48CL supports the Power over Camera Link (PoCL) functionality with SafePower and is able to provide power to PoCL enabled cameras via the Camera Link data cable thereby removing the need for a separate power supply. Conventional non-PoCL cameras are still supported.
ROI and sub-sampling controls are used to increase application processing speed by only storing the required data. In addition the LUT functionality provides support for gamma correction, dynamic range cropping and binary thresholding in real time. The DataMapper further reduces the load on the host processor by mapping and packing the acquired data prior to transfer across the PCI bus. For example, the acquired data can be mapped into a suitable format and transferred directly to the graphics display, without the need for any host processing.
The PCI interface comprises intelligent scatter-gather hardware which reads its instructions direct from memory without any host CPU intervention. This in turn controls the DMA engine, which transfers the packed video data into any target memory which can be reached from the PCI bus. This can be system memory, graphics memory, or even other devices on the same or other PCI busses, such as DSP cards, etc.
The majority of the functionality is implemented in a single FPGA (Field Programmable Gate Array) providing a flexible solution for interfacing to Camera Link compliant sources. The FPGA implements the PCI interface, hardware scatter-gather control, PCI Initiator Burst Control (DMA), Acquisition Control, Region of Interest (ROI) and sub-sampling control, DataMapping functions, Datapath FIFOs, and Counter/Timer support. In addition the board contains Look Up Table (LUT) functionality, a dual Universal Asynchronous Receiver Transmitter (UART), 4 bit opto-isolated I/O, two 2 bit differential input ports and two 8 bit TTL I/O ports. All I/O is accessible on the J2 connector.
The PHX Software Development Kit (SDK), available as a separate item, allows rapid system development and integration. It provides comprehensive example applications and optimized libraries, and is available for a variety of operating systems via a common API, including Windows and Linux (32 bit and 64 bit environments) as well as Mac OS X, DOS and QNX. Drivers for third party applications are also available, Common Vision Blox, StreamPix, LabVIEW etc. As well as functions that control the hardware, the libraries include general purpose functions for the manipulation and display of images. A separate datasheet describes the SDK in detail.
|Buffer:||64 K FIFO|
|Camera Inputs:||2 Base, or 1 Medium|
|Interface :||Camera Link|
|Pixel Clock:||60 MHz|